Development of mobile computing requires a silicon chip to have a radio frequency communication function (RF communication function). A conventional silicon chip has therein CMOS gates including CMOS transistors, wherein signal processing is performed only in a digital logic processing scheme using the CMOS gates. On the other hand, the RF communication function is directed to analog signal processing, and includes an amplifying function for a received wave by using passive elements such as inductors, and a transmitting function using pulse generator, pulse delay circuit etc., in addition to an analog processing function of the CMOS transistors, such as an analog signal amplification function.
More specifically, a communication terminal includes in a silicon semiconductor chip, as shown in FIG. 26, at least a RF communication circuit area 61 including a LNA (Low noise amplifier) 61a, a transmission signal generating circuit 61b and a switch circuit 61c, and a digital baseband (BB) area 62 including an A/D converter 62a for converting those analog signals into digital signals, a digital signal processing circuit 62b, and a D/A converter for again converting the digital signals, for which signal processing is performed, into analog signals. Although a memory area such as SRAM and DRAM is needed therein in fact, it is not depicted in the figure.
The amplifying function of the CMOS transistors is significantly improved along with the development of the micro-fabrication technique, to the extent that enables the analog signal processing in the RF area. However, the analog circuit requires an LCR circuit configuration, and there are technical problems in development of the high-performance and small-size inductors formed on the silicon semiconductor chips, whereby the practical application thereof is delayed. FIG. 27 shows a schematic top plan view of an inductor formed on a silicon semiconductor chip and an equivalent circuit thereof. The inductor is formed by using multi-layered interconnects formed on the silicon semiconductor chip.
If the loss of the inductor is neglected, the inductance L of the inductor is expressed by the following formula (1):L∝μ×n2×r  (1),where μ, n and r are permeability of the inductor-formed area, number of windings and a maximum radius of the windings, respectively.
A silicon oxide film is used for the isolation between the multi-layered interconnects, and the permittivity can be assumed as the permittivity μ0 of vacuum. According to the formula (1), it is necessary to adopt n=26 as the number of windings and around 2r=250 μm as one side of the inductor, for obtaining L=100 nH. Although this is an extremely small size compared to the off-chip inductor part, it occupies a large area in the normal logic chip. Thus, it is difficult to use a large number of inductors in the RF circuit. Increase of the inductance L without changing the size of the inductor can be achieved by raising the permeability of the inductor-formed area. The formula (1) shows this is achieved by adopting a high-permeability material.
In the formula (1), the inductance (L) of the inductor is noticed. The inductor has a power loss factor, as shown by the equivalent circuit on the silicon semiconductor chip in FIG. 27, which impedes the high-frequency characteristic of the circuit. For example, the resistance (Rs) of the inductor line configured by the multi-layered interconnects causes a large power dissipation because a large-size inductor has an increased line length. In addition, the loss by charge/discharge of the coupling capacitance (Cp) between the lines of the inductor, the loss by the coupling capacitance (Cox/2) between the inductor and the silicon semiconductor substrate, and the loss caused by the p-n junction capacitance in the silicon substrate are the causes of the large power dissipation.
As another factor other than the above losses, there is a noise propagation via the silicon substrate and the loss thereof, which is incurred by an induction current (eddy current) due to the fluctuation of the high-frequency magnetic field from the inductor. The noise propagation phenomenon is a technical problem common to the RF circuits formed on the silicon semiconductor substrate as well as the inductor. For reducing the substrate noise, it is important to increase the substrate resistance (R1) and reduce the substrate capacitance (C1). It is to be noted that the substrate resistance R1 is determined by the specific resistance ρ and the substrate thickness tsub.
Under the technical background as described above, the technical development for forming a high-performance inductor on the silicon semiconductor substrate has been advanced. A first conventional technique is such that a groove (trench) is formed on a silicon substrate in an inductor-forming area and filled with a silicon oxide etc. (refer to, for example, JP-A-2000-77610, 2002-93622 and 2000-40789).
FIG. 28 is a sectional view of the on-chip inductor proposed in JP-A-2000-77610. As shown in the same figure, lattice-like trenches are formed on a silicon substrate 71 and filled with a silicon oxide film 72, and an inductor 73 is formed on the resultant trench-forming area. Embedding the silicon oxide film 72 within the silicon substrate 71 reduces the capacitance (C1) of the inductor-formed area and the coupling capacitance (Cox/2) between the inductor line and the substrate, thereby achieving reduction of the leakage current and inductive current of the inductor.
JP-A-2002-93622 describes an element wherein a spiral trench is formed on a silicon substrate in the gaps between spiral lines of the inductor and the outer periphery thereof, and the trench is filled with an insulating material (silicon oxide).
JP-A-2000-40789 describes a technique wherein an inductor is formed using multi-layered interconnects on a silicon substrate, and an opening formed from the surface of the silicon substrate is filled with an insulator (silicon dioxide, or silicon nitride) and an intrinsic silicon, whereby a plate-like insulating film and a shallow-trench insulating film are alternately formed from the surface of the silicon substrate toward the internal of the substrate in the inductor-formed area.
The techniques as described above are such that the silicon substrate is drilled from the surface thereof and the internal of the resultant structure is filled with an insulator.
As a second conventional technique, it is proposed to increase the permeability of the periphery of the windings by embedding a ferromagnetic or soft magnetic material within the inductor-forming area, thereby increasing the inductance (refer to, for example, JP-A-2001-284533). More specifically, JP-A-284533 describes a technique wherein windings of an inductor 83 are formed in an insulating film 82 on a silicon substrate 81, and a magnetic core 84 made of a ferromagnetic substance such as an iron-cobalt alloy is disposed in the insulating film in the central area (and the peripheral area) of the windings, as shown in FIG. 29.
JP-A-2001-285433 describes a technique for reducing the resistance of an inductor line by connecting together a first interconnect layer and a second interconnect layer and thus using a plurality of interconnect layers.